View MIC7400-0005YFL_9095478.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

mic74 2- wire serial i/o expander and fan controller smbus is a trademark of intel corporation. i 2 c is a trademark of phillips electronics n.v. micrel inc . ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 (408) 944 - 0800 ? fax + 1 (408) 474 - 1000 ? http://www.micrel.com september 30 , 20 14 revision 3.0 general description the mic74 is a fully programmable serial - to - parallel i/o expander compatible with the smbus? (system manage - ment bus) protocol. it acts as a slave on the bus, providing eight independent i/o lines. each i/o bit can be individually programmed as an input or output. if programmed as an output; each i/o bit can be programmed as an open - drain or complementary push - pull output. if desired, the four most significant i/o bits can be programmed to implement fan speed control. an internal clock g enerator and state machine eliminate the overhead generally associated with bit - banging fan speed control. programming the device and reading/writing the i/o bits is accomplished using seven internal registers. all registers can be read by the host. output bits are capable of directly driving high - current loads, such as leds. a separate interrupt output can notify the host of state changes on the input bits without requiring the mic74 to perform a transaction on the serial bus or be polled by the host. th ree address selection inputs are provided, allowing up to eight devices to share the same bus and provide a total of 64 bits of i/o. the mic74 is available in an ultra - small - footprint 16 - pin qsop. low quiescent current, small footprint, and low package height make the mic74 ideal for portable and desktop applications. datasheets and support documentation are available on micrels web site at : www.micrel.com . features ? provides eight bits of general purpose i/o ? built - in fan speed control logic (optional) ? 2- wire smbus?/i 2 c? - compatible serial interface plus interrupt output ? 2.7v to 3.6v operating voltage range ? 5v - tolerant i/o ? low quiescent current: 2a (typical) ? bit - programmable i/o options: ? input or output ? push - pull or op en - drain output ? interrupt on input changes ? outputs can directly drive leds (10ma i ol ) ? up to 8 devices per bus applications ? general purpose i/o expansion via serial bus ? personal computer system management ? distributed sensing and control ? microcontroller i/o expansion ? fan control typical application downloaded from: http:///
micrel, inc. mic74 september 30 , 20 14 2 revision 3.0 ordering information part number junction temperature range package lead finish mic74yqs C 40 c to +85 c 16 - pin qsop pb-free pin configuration 16 - pin qsop ( qs) (top view) pin description pin number pin name pin function 1 , 2, 3 a0, a1, a2 address (input): slave address selection inputs; sets the three least significant bits of the mic 74s slave address. 4, 5, 6, 7 p0, p1, p2, p3 parallel i/o (input/output): general - pu rpose i/o pin. direction and output type are user - programmable. 8 gnd ground 9, 10, 11, 12 p4, p5, p6, p7 (/shdn, /fs0 /fs1, /fs2) parallel i/o (input/output): p4 C p7 are general - purpose i/o pins. direction and output type are user - programmable. shutdown (output): when the fan bit is set, pin 9 becomes shdn. fan speed (output): when the fan bit is set, pins 10 through 12 become /fs0 C /fs2 respectively, controlled by the fan_speed register. 13 /alert interrupt (o utput): active - low, open - drain output signals input - change - inter rupts to the h ost on this pin. signal is cleared when the bus master (host) polls the ara (alert response address = 0001 100) or reads status. 14 clk serial bus clock (input): the host provides the serial bit clock in this input. 15 data serial data (input/output): se rial data input and open - drain serial data output. 16 vdd power supply (input). downloaded from: http:///
micrel, inc. mic74 september 30 , 20 14 3 revision 3.0 absolute maximum ratings ( 1 ) supply voltage (v dd ) ................................................... + 4.6 v input voltage [all pins except vdd and gnd] (v in ). .................................. gnd C 0.3v to +5.5 v junction temperature (t j ) ......................................... 150c lead temperature (soldering, 10s) ............................ 260c esd rating ( 3 ) vdd ...................................................................... 1.5 kv a0, a1, a2 .............................................................. 500v others .................................................................... 200v operating ratings ( 2 ) supply voltage (v dd ) .................................... +2.7v to +3.6 v ambient temperature (t a ) .......................... C 40c to +85c package thermal resistance ( ja ) ........................ 163 c/w electrical characteristics ( 4 ) 2.7v v dd 3.6v; t a = 25c, bold values indicate C 40c < t a < +85c, unless noted. symbol parameter condition min . typ . max . units v in input voltage ( any pin e xcept v dd and gnd ) gnd C 0.3 5.5 v i dd operating supply current p[7:0] inputs; p[7:0] = v dd or gnd /alert open; f clk = 100khz 2 6 a i start fan startup supply current (fan mode only) during t start ; /alert, /shdn, /fs2[2:0] = open; v clk = v data = v dd ; p[ 3:0] = inputs 1.75 ma i stby standby supply current / alert = open, v clk = v data = v dd ; p[3:0] = inputs 1 3 a serial i/o (data, clk) v il input low voltage C 0.3 0.8 v v ih input high voltage 2 5.5 v v ol output low voltage i ol = 3ma 0.4 v i leak leakage current v in = 5.5v or gnd C1 +1 a c in input capacitance 10 pf notes: 1. exceeding the absolute maximum ratings may damage the device. 2. the device is not guaranteed to function outside its operating ratings. 3. devices are esd sensitive. handling precautions are recommended. human body model, 1.5k ? in series with 100pf. 4. specification for packaged product only. 5. devices participating in a transfer will timeout when any clock low exceeds the value of t timeout(min) of 25ms. devices that have detected a timeout condition must reset the communication no later than t timeout(max) of 35ms. the maximum value specified must be adhered to by both a master and a slave as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms). 6. t high(max) provides a simple guaranteed method for de vices to detect bus idle conditions. 7. rise and fall time is defined as follows: t r = v il(max) C 0.15v to v ih(min) + 0.15v; t f = 0.9v dd to v il(max) C 0.15v. 8. guaranteed by design. downloaded from: http:///
micrel, inc. mic74 september 30 , 20 14 4 revision 3.0 electrical characteristics ( 4 ) (continued) parallel i/o [p0 C p3, p4(/shdn), p5(/fs0) Cp7(/fs2)] symbol parameter condition min . typ . max . units v il input low voltage C 0.5 0.8 v v ih input high voltage 2 5.5 v i ol output low current v ol = 0.4v, v dd = 2.7v 7 ma v ol = 1v, v dd = 3. 3v 10 ma i oh output high current v oh = 2.4v 7 ma i leak leakage current v in = 5.5v or gnd C1 +1 a c in input capacitance 10 pf c out output capacitance 10 pf address input (a0 C a2) v il input low voltage C 0.3 0.3v dd v v ih input high voltage 0.7v dd v dd +0.3 v i leak leakage current v in = v dd or gnd C 250 +250 na /alert v ol output low voltage i ol = 1ma 0.4 v i leak leakage current v in = v dd or v ss C1 250 +1 a ac characteristics t start fan startup interval n ormal operation 0.5 1 3.3 se c t pulse minimum pulse - width m inimum pulse - width on p n to generate an interrupt, note 8 10 ns t /int interrupt delay i nterrupt delay from state change on p n to /alert v ol , note 8 4 s t /ir delay from status read or ara response to /alert v oh 4 s t hd:sta hold time, note 8 h old time after repeated start conditi on , after this period, the first clock is generated 4 s t su:sta setup time, note 8 r epeated start condition setup time 4.7 s t su:sto stop condition setup time note 8 4 s t hd:dat data hold time note 8 500 ns t su:dat data setup time note 8 0 ns t timeout clock low time - out note 5 , 8 25 35 ms t low clock low period note 6 , 8 4.7 s t high clock high period note 6 , 8 4 50 s t f clock/data fall time note 7 , 8 300 ns t r clock/data rise time note 7 , 8 1000 ns t buf bus free time between stop and start condition note 8 4.7 s downloaded from: http:///
micrel, inc. mic74 september 30 , 20 14 5 revision 3.0 timing definitions register descriptions tabl e 1 . device configuration register dev_cfg d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] always write as zero fan ie device configuration register parameters ? power - on default value: 0000 0000 b , 00 h ? interrupts disabled ? not in fan mode ? command _ byte address: 0000 0000 b , 00 h ? type: 8 - bits, read/write ? bit name: ie ? function: global interrupt enable ? operation: 1 = enabled; 0 = disabled ? bit name: fan ? function: selects fan mode (p[7:4] vs. /fs[2:0], /shdn) ? operation: 1 = fan mode; 0 = i/o mode ? bit name: d[2] through d[6] ? function: reserved ? operation: reserved; always write as zero table 2 . data direction register dir d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] dir7 dir6 dir5 dir4 dir3 dir2 dir1 dir0 data direction register parameters ? power - on default value: 0000 0000 b , 00 h ? all p n s configured as inputs ? command_byte address: 0000 0001 b , 01 h ? type: 8 - bits, read/write ? bit name: dir n ? function: selects data direction, input or output, of p n ? operation: 1 = output; 0 = input ? notes: if the fan bit of the dev_cfg register is set to 1 (i.e., if fan mode is selected), p[7:4] are automatically configured as open - drain outputs. they are then referred to as /fs[2:0] and /shdn. the dir register has no effect on these i/o bits while in fan mode. ? downloaded from: http:///
micrel, inc. mic74 september 30 , 20 14 6 revision 3.0 register descriptions (continued) table 3 . output configuration register out_cfg d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] out7 out6 out5 out4 out3 out2 out1 out0 output configuration register parameters ? power - on default value: 0000 0000 b , 00 h ? all outputs open - drain ? command_byte address: 0000 0010 b , 02 h ? type: 8 - bits, read/write ? bit name: out n ? function: selects output driver configuration of p n when p n is configured as an output. ? operation: 1 = push - pull; 0 = open - drain ? notes: if the fan bit of the dev_cfg register is set to 1 (i.e., if fan mode is selected), p[7:4] are automatically configured as open - drain outputs. they are then referred to as /fs[2:0] and /shdn. the out_cfg register has no effect on these i/o bits while in fan mode. table 4 . status register status d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] s7 s6 s5 s4 s3 s2 s1 s0 status register parameters ? power - on default value: 0000 0000 b , 00 h ? no interrupts pending ? command_byte addr ess: 0000 0011 b , 03 h ? type: 8 - bits, read/write ? bit name: s n ? function: flag for p n input - change event when p n is configured as an input. s n is set when the corresponding input changes state. ? operation: 1 = change occurred; 0 = no change occurred ? notes: if the fan bit of the dev_cfg register is set to 1 (i.e., if fan mode is selected), p[7:4] are automatically configured as open - drain outputs. they are then referred to as /fs[2:0] and /shdn. no interrupts of any kind are generated by these pins while in fan mode. all status bits are cleared after any read operation is performed on status. table 5 . interrupt mask register int_mask d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] im7 im6 im5 im4 im3 im2 im1 im0 interrupt mask register par ameters ? power - on default value: 0000 0000 b , 00 h ? command_byte address: 0000 0100 b , 04 h ? type: 8 - bits, read/write ? bit name: im n ? function: interrupt enable bit for p n when p n is configured as an input. ? operation: 1 = enabled; 0 = disabled ? notes: if the fan bit of the dev_cfg register is set to 1 (i.e., if fan mode is selected), p[7:4] are automatically configured as open - drain outputs. they are then referred to as /fs[2:0] and /shdn. no interrupts of any kind are generated by these pins while in fan mode. downloaded from: http:///
micrel, inc. mic74 september 30 , 20 14 7 revision 3.0 register descriptions (continued) table 6 . data register data d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] p7 p6 p5 p4 p3 p2 p1 p0 data register parameters ? power - on default value: 1111 1111 b , ff h ? command_byte address: 0000 0101 b , 05 h ? type: 8 - bits, read/write ? bit name: p n ? function: returns the current state of any p n configured as an input and the last value written to p n s configured as outputs. writing the data register sets the output state of any pns configured as outputs; writes to i/o bits configured as inputs are ignored. ? read operation: 1 = p n is high; 0 = p n is low ? write operation: 1 = p n is set to 1; 0 = p n is cleared ? notes: if the fan bit of the dev_cfg register is set to 1 (i.e., if fan mode is selected), p[7:4] ar e automatically configured as open - drain outputs. they are then referred to as /fs[2:0] and /shdn. the state of these pins is determined by the fan_speed register. while in fan mode, d[7:4] of the data registers have no effect. table 7 . fan speed register fan_speed d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] always write as zero fan speed fan speed register parameters ? power - on default value: 0000 0000 b , 00 h ? fan off ? command_byte address: 0000 0110 b , 06 h ? type: 8 - bits, read/write ? bit name: d[0] through d[2] ? function: determines bit - pattern on fs[2:0] ? operation: fan speed settings (see below) d[2:0] value output state fan speed /fs[2:0] /shdn 000 111 0 off 001 110 1 speed 1 (slowest) 010 101 1 speed 2 011 100 1 speed 3 100 011 1 speed 4 101 010 1 speed 5 110 001 1 speed 6 111 000 1 speed 7 (fastest) ? notes: any time the fan speed register contains zero, meaning the fan is shut down, and a non - zero value is written into the fan speed register, the /fs[2:0] and /shdn outputs w ill assume the highest fan speed state for approximately one second (tstart). following this interval, the state of the fan speed control outputs will assume the value indicated by the contents of fan_speed. this insures that the fan will start reliably when low speed operation is desired. ? bit name: d[3] through d[7] ? function: reserved ? operation: always write as zero downloaded from: http:///
micrel, inc. mic74 september 30 , 20 14 8 revision 3.0 functional diagram typical i/o port (fan speed control logic not shown) functional description pin descriptions vdd power supply input connection. see operating ratings section for additional information. gnd ground or return connection for all mic74 functions . clk a clk signal is provided by the host (master) and is common to all devices on the bus. the clk signal controls all transactions in both directions on the bus and is applied to each mic74 at the clk pin. data serial data is bidirectional and is common to all devices on the bus. the mic74s data output is open - drain. the data line requires one external pull - up resistor or current source per system that can be located anywhere along the line. a2, a1, a0 the mic74 responds to its own unique address which is assigned using the a0 C a2 pins. a0 C a2 set the three lsbs (least significant bits) of the mic74s 7 - bit slave address. the three address pins allow eight unique mic74 addresses in a system. when the mic74s address matches an address received in the serial bit stream, communication is initiated. a2, a1 and a0 should be connected to gnd or vdd. the state of these pins is sampled only once at device power - on. new slave addresses are not accepted unless the mic74 is powered off then on. table 8 . mic74 address configuration inputs mic74 slave address a2 a1 a0 binary he x 0 0 0 010 0000 b 20 h 0 0 1 010 0001 b 21 h 0 1 0 010 0010 b 22 h 0 1 1 010 0011 b 23 h 1 0 0 010 0100 b 24 h 1 0 1 010 0101 b 25 h 1 1 0 010 0110 b 26 h 1 1 1 010 0111 b 27 h downloaded from: http:///
micrel, inc. mic74 september 30 , 20 14 9 revision 3.0 alert response address the mic74 also responds to the alert response address (ara). the ara is used by the master (host) to request the address of a slave that has provided an interrupt to the master via the /alert line. the ara is a single address (0001 100) common to all slaves and is described in more detail under interrupt generation with related information under /alert . also see figure 7 . pn, /shdn, and /fs0 - /fs2 p0 through p7 are general - purpose input/outp ut bits. each bit is independently programmable as an input or an output. if programmed as an output, each bit is further programmable as either a complementary push - pull or open - drain output. if properly enabled, any p n programmed as an input will generat e an interrupt to the host using the /alert output when the input changes state. in this way, the mic74 can notify the host of an input change without requiring periodic polling by the host or a message transaction on the bus. regardless of whether interrupts are enabled or disabled, each input - change event also sets the corresponding bit in the status register. i/o configuration is performed using the output configuration (out_cfg), i/o direction (dir), and interrupt mask (int_mask) registers. if the fan bit in the device configuration register is set, the states of p[7:4] are controlled by the fan_speed register. the bits in the out_cfg, dir, and int_mask registers corresponding to p[7:4] are ignored. when in fan m ode, p[7:4] are referred to as /fs2, /fs1, /fs0, and /shdn. while in this mode, no interrupts of any kind will be generated by these pins. /alert the alert signal is an open - drain, active - low output. the operation of the /alert output is controlled by the im n bits in the int_mask register and the global interrupt enable bit (ie) in the dev_cfg register. if the ie bit is set to zero, or if the corresponding interrupt enable bit, im n , is set to zero, no input - change interrupts will be generated. regardless of the ie bit setting, the change will be re flected in the status register. if the ie bit is set to one, im n is set to one, and p n is an input, then /alert is driven active whenever p n changes state, (goes from a high - to - low or low - to - high state). once triggered, /alert is unconditionally reset to i ts inactive state once the mic74 successfully responds to the alert response addressor status is read. serial port operation the mic74 uses standard smbus read_byte and write_byte operations to communicate with its host. the read_byte operation is a composite read - write operation consisting of first sending the mic74s slave address followed by a command byte (a write) and then resending the slave address and clocking out the data byte (a read). the command byte is the address of the target register. see table 9 . an example of a read_byte operation is shown in figure 8 . similarly, the write - byte operation consists of sending the devices slave address followed by a command by te and the byte to be written to the target register. again, in the case of the mic74, the command byte is the address of the target register. see table 9 . in addition, to the read byte and write byte protocols, th e mic74 adheres to the smbus protocol for response to the ara (alert response address). an mic74 expects to be interrogated using the ara when it has asserted its /alert output. /alert interrupts can be enabled or disabled using the ie bit in the dev_cfg r egister. power - on when power is initially applied, the mic74s internal registers will assume their power - up default state and the state of the address inputs, a2, a1 and a0, will be read to establish the devices slave address. see the individual register descriptions for each registers default state. also see table 9 . i/o ports each i/o bit, p0 through p7, may be individually programmed as an input or output using the corresponding bit in the i/o direction registe r, dir. if programmed as an output, each is further programmable as either a complementary push - pull or open - drain output using the output configuration register, out_cfg. if enabled by the corresponding bit, im n , in the interrupt mask register int_mask, each p n programmed as an input will generate an interrupt to the host on /alert if the input changes state. in this way, the mic74 can notify the host of an input change without requiring periodic polling by the host or a transaction on the bus. each input - change event also sets the corresponding bit in the status register, status. see functional diagram for the logic arrangement of atypical mic74 i/o port. fan speed control if the fan bit in the device configuration register is set, the state of p[7:4] is controlled by the fan_speed register. the bits in the out_cfg, dir, and int_mask registers corresponding to p[7:4] are ignored. when in fan control mode, p[7:4] are referred to as /fs2, /fs1, /fs0, and /shdn. while in this mode, no interrupts of any kind will be generated by these pins. see application information for typical fan speed control applications. downloaded from: http:///
micrel, inc. mic74 september 30 , 20 14 10 revision 3.0 table 9 . register summary register name register description address available options power - on default binary hex binary hex dev_cfg device configuration 0000 0000 b 00 h 8- bit read/write 0000 0000 b 00 h dir i/o direction 0000 0001 b 01 h 8- bit read/write 0000 0000 b 00 h out_cfg output config uration 0000 0010 b 02 h 8- bit read/write 0000 0000 b 00 h status interrupt status 0000 0011 b 03 h 8- bit read 0000 0000 b 00 h int_mask interrupt mask 0000 0100 b 04 h 8- bit read/write 0000 0000 b 00 h data general purpose i/o 0000 0101 b 05 h 8- bit read/write 1111 1111 b ff h fan_speed fan speed 0000 0110 b 06 h 8- bit read/write 0000 0000 b 00 h fan start - up any time the fan speed register contains zero (fan is off) and then a nonzero value is written to fan_speed, the /fs[2:0] and /shdn outputs will assume the highest fan speed state for approximately one second (t start ). following this interval, the state of the fan speed control outputs will assume the value indicated by the contents of fan_speed. this insures that the fan will start reliably when low speed operation is desired. the t start interval is generated by an internal oscillator and counters. at the end of t start , this oscillator is powered down to reduce overall power consumption. figure 1 . fan speed control application proper sequencing of the /fs[2:0] and /shdn signals is performed by the mic74s internal logic state machine. when activating the fan from the off state, the /fs[2:0] lines change state first, then, after a delay equal to one - half of t start , the /shdn pin is deasserted. conversely, when the fan is shutdown (zero is written to fan_speed), the /shdn pin is deasserted first. the /fs[2:0] lines are subsequently deasserted after a delay of 1?2t start . the internal oscillator is also powered down following the t start /2 interval at fan shut - down. these timing relationships are illustrated in figure 2 . interrupt generation assuming that any or all of the i/os are configured as inputs, the mic74 will reflect the occurrence of an input change in the corresponding bit in the status register, status. this action cannot be masked. an input change will only generate an interrupt to the host if interrupts are properly configured and enabled. the mic74 can operate in either polled mode or interrupt mode. in the case of polled operation, the host periodically reads the contents of status to determine the device state. the act of reading status clears its contents. repeating events which have occurred since the last read from status will not be discernable to the host. interrupts are only generated if the global interrupt enable bit, ie, in the dev_cfg register is set. the /alert signal will be asserted (driven low) when an interrupt is generated. the mic74 expects to be interrogated using the ara when it has generated an interrupt output. once it has successfully responded to the ara (alert response address), the /alert output will be deasserted. the contents of the status register will not be cleared until it is read using a read byte operation. if a given system does not wish to use the smbus ara protocol for reporting interrupts, the system may simply poll the contents of the status register after detecting an interrupt on /alert. this action will clear the contents of status and cause /alert to be deasserted. re ading the status register is an acceptable substitute for using the ara protocol. presumably, however, it will involve higher system overhead since all the devices on the bus must be polled to determine which one generated the interrupt. downloaded from: http:///
micrel, inc. mic74 september 30 , 20 14 11 revision 3.0 figure 2 . typical mic74 fan mode timing and system behavior downloaded from: http:///
micrel, inc. mic74 september 30 , 20 14 12 revision 3.0 application information bit transfer the data received on the data pin must be stable during the high period of the clock . figure 3 . acceptable bit transfer conditions data can change state only when the clk line is low. refer to the figure above. start and stop conditions tw o unique bus situations define start and stop conditions. a high - to - low transition of the data line while clk is high indicates a start condition. a low - to - high transition of the data line while clk is high defines a stop condition. see figure 4 . figure 4 . start and stop definitions start (leading edge of start) and stop (trailing edge of stop ) conditions are always generated by the bus master (host). after a start condition, the bus is considered to be busy. the bus becomes free again after a certain time following a stop condition or after both clk and data lines rema in high for more than 50s. serial byte format every byte consists of 8 bits. each byte transferred on the bus must be followed by an acknowledge bit. bytes are transferred with the msb (most significant bit) first. see figure 5 . figure 5 . serial byte format acknowledge and not acknowledge the acknowledge related clock pulse is generated by the master. the transmitter releases the data line (high) during the acknowledge clock cycle. in order to acknowledge (ack) a byte, the receiver must pull the data line low during the high period of the clock pulse according the bus timing specifications. a slave device that wishes to not acknowledge a byte must let the data line remain high during the acknowledge clock pulse. see figure 6 . figure 6 . acknowledge and not acknowledge downloaded from: http:///
micrel, inc. mic74 september 30 , 20 14 13 revision 3.0 figure 7 . interrupt handling using the alert response address fig ure 8 . interrupt handling without the alert response address downloaded from: http:///
micrel, inc. mic74 september 30 , 20 14 14 revision 3.0 initializing the mic74 the mic74s internal registers are reset to their default state at power - on. the mic74s default state can be summarized as follows: ? all i/os c onfigured as inputs (dir = 00 h ) ? output configuration set to open - drain (out_cfg = 00 h ) ? all outputs high/floating (data = ff h ) ? fan functions disabled (fan_speed = 00 h ; fan bit of dev_cfg = 0) ? all interrupts masked (ie bit of dev_cfg = 0) the result of this configuration is that all i/o pins will essentially float unless driven by external circuitry. any system using the mic74 will need to initialize the internal registers to the state required for proper system operation. the recommended order for initializing the mic74s registers is as follows: figure 9 . initializing the mic74 for polled operation 1. write data 2. write out_cfg 3. write dir 4. write fan_speed (if using fan mode) 5. write int_mask (if using interrupts) 6. read status to clear it 7. wr ite dev_cfg to enable fan mode and/or interrupts, if using. at the co nclusion of step three, any i/os configured as outputs in step 2 will be driven to the levels programmed into the data register in step one. the order of step 1 through step 3 is importan t to e nsure that spurious data does not appear at the i/os during configuration. following step 7, programming the device configuration register, the mic74 will begin generating interrupts if they are enabled, and the fan will be started if fan_speed contains a non - zero value. the corresponding interrupt service routines (if any) must be initialized and enabled prior to step 7 . status should be cleared (step 6) in both polled and interrupt driven systems. figure 10 . initializing t he mic74 for interrupts downloaded from: http:///
micrel, inc. mic74 september 30 , 20 14 15 revision 3.0 polled mode input state changes on i/os configured as inputs will be reflected in the status register regardless of the state of the global interrupt enable bit (ie) and the individual interrupt mask bits in int_mask. in a system utilizing polling to monitor for input changes, the status register is periodically read to check for input events. the act of reading status clears it in preparation for detecting future events. the status bits corresponding to i/os configured as outputs or corresponding to p[7:4] when in fan mode will not be set by state changes on these pins. it is always good practice, however, to mask the value obtained when reading status to eliminate any bits, output or otherwise, that are not of immediate concern. t his will help avoid problems if software changes are made in the future. the flowchart shown in figure 9 illustrates the steps involved in initializing the mic74 for polled operation. the flowchart in figure 11 illustrates the corresponding polling routine. the process for writing output data is straight - forward simply write the desired bit pattern to data. special precautions may be required when changing output data in an interrupt driven system, however. see the writing to the data register section. interrupt mode input state changes on i/os configured as inputs will be reflected in the status register regardless of the state of t he global interrupt enable bit (ie) and the individual interrupt mask bits in int_mask. in a system utilizing interrupts to detect input changes, one or more of the bits in the interrupt mask register, int_mask, are set to allow interrupts on /alert to be generated by input events. the global interrupt enable bit, ie, in the device configuration register must also be set to enable interrupts. the flowchart shown in figure 10 illustrates the steps involved in initial izing the mic74 for interrupt - driven operation. the flowchart in figure 12 illustrates the corresponding interrupt service routine using the smbus ara. the corresponding timing diagram is shown in figure 7 . the flowchart in figure 13 illustrates the corresponding interrupt service routine using polling to determine the interrupt source. figure 8 illustrates the timing. utilizing the ara greatly speeds identification of the interrupting slave device and lowers latency, as only a single transaction on the bus is necessary to identify the interrupt source. using either method, status must be read to determine the exact source of the interrupt within the mic74. figure 11 . polling the mic74 downloaded from: http:///
micrel, inc. mic74 september 30 , 20 14 16 revision 3.0 the act of reading status clears it in preparation for detecting future events. the status bits corresponding to i/o s configured as outputs or corresponding to p[7:4] when in fan mode will not be set by state changes on these pins. it is always good practice, however, for the interrupt service routine to mask the value obtained when reading status to eliminate any bits, output or otherw ise, that are not of immediate concern. this will help avoid problems if software changes are made in the future. the process for writing output data is straight - forward simply write the desired bit pattern to data. special precautions may be required, however, when changing output data in an interrupt driven system. see the writing to the data register section. figure 12 . interrupt service routine using the ara writing to the data regis ter multiple software routines may use the various output bits available on the mic74 to control individual functions such as power switches, leds, etc. these various functions may be handled by independent software routines that must manipulate individual output bits without regard for other bits. care must be taken to ensure that these various software routines do not interfere with each other when modifying output data. the recommended procedure for changing isolated output bits is as follows: 1. read data 2. set desired bits by oring the value read from data with an appropriate mask value 3. clear desired bits by anding the value read from data with an appropriate mask value 4. write the result back to data a functionally equivalent alternative to this procedure is to keep an image of the data register in software. any independent routines would make changes to this image using the procedure above and then call a routine that actually writes the new image to data. interrupts would be disabled briefly while data is being modified. figure 13 . interrupt service routine without ara downloaded from: http:///
micrel, inc. mic74 september 30 , 20 14 17 revision 3.0 regardless of which procedure is used, it is important that only one software routine at a time attempts to make changes to the output data. in a system where polling is the exclusive method for servicing inputs, this is usually not a problem. if interrupts are employed to any degree in dealing with mic74 inputs, care must be taken to e nsure that a software routine in the midst of making changes to outputs is not interrupted by another routine that proceeds to make its own changes. the risk is that the value in data will be changed by an interrupting routine after it is read by a different routine in the process of making its own changes. if this occurs, the value written to data by the first routine may be incorrect. the most straight forward solution to this potential problem is to disable system interrupts while the data register is actually being modified. application circuits the mic74, in conjunction with a linear l ow - dropout or switching regulator, can be configured as a fan speed controller. most adjustable regulators have a feedback pin and use an external resistor divider to adjust the output voltage. the mic74 is designed to take advantage of this configuration with its ability to manipulate multiple feedback resistors connected to the p4 C p7 outputs. individual open - drain output bits are selectively grounded or allowed to float under the control of the internal state machine. this action raises or lowers the equi valent resistance seen in the regulators feedback path, thus changing the output voltage. any conventional adjustable regulator is usually suitable for use with the mic74. the output voltage correspond ing to each value to be programmed into the fan speed register can be determined by selecting the resistors in the circuit. the regulator itself can be chosen to meet the needs of the application, such as input voltage, output voltage, current handling capability, maximum power dissipation, and physical spac e constraints. two circuit examples are shown below. the circuit of figure 14 illustrates use of a typical ldo linear regulator such as the mic29152. a switching regulator - based fan control circuit using the mic457 4 200khz simple 0.5a buck regulator is shown in figure 15 . both circuits assume a 12v fan power supply but will accommodate much higher input voltages if required (mic4574: 24v, mic29152: 26v). care must be taken, however, to ensure that the maximum power dissipation of the regulator is not exceeded. if the regulator overheats, its internal thermal shutdown circuitry will deactivate it. (see mic29152 or mic4574 datasheet.) because the mic74 pow ers up with all its i/ o s inputs (floating), both circuits will power - up with the fan running at a minimum speed determined by the value of rmin_speed. once the mic74s fan mode is activated by setting the appropriate bit in the configuration register figure 14 . fan speed control using an adjustable low - dropout regulator figure 15 . fan speed control using a buck converter downloaded from: http:///
micrel, inc. mic74 september 30 , 20 14 18 revision 3.0 the fan will be shutdown by the assertion of the /shdn output if fan_speed is zero. if fan_speed is pr ogrammed with any nonzero value, the fan will be driven to its maximum speed for the duration of tstart (about 1 second) and then assume the programmed speed. note that the circuit in figure 15 contains an addition al transistor, q1, as an inverter because the regulator in this example has an active - high shutdown input rather than an enable input. otherwise the circuits function identically. table 10 lists the output voltages corresponding to all the fan speeds and system states possible with these circuits. the following equations are used to calculate the resistor values used in mic74 fan speed control circuits. it is assumed here that the regulators internal reference voltage is 1.24v. if the regulator uses a different reference voltage, that value should be used instead. the following equations show how to calculate the resistor values for the fan controllers. for example, when the fan speed register contains 011 b , which is the third low est speed, r f1 and r f0 are parallel to r min to give the equivalence resistor (r eq ) value of 545?. r eq = rf1 || rf0 || rmin r eq = 1.8k || 3.6k || 1k r eq = 545 the output voltage is calculated by using: ? ?? ? ? ?? ? + = eq fb out r r 1 1.24v v ?? ? ?? ? + = 545 3k 1 1.24v v out v out = 8.06v table 10 . fan speed selection fan_speed value fan speed selected r fb r min r f2 r f1 r f0 r eq v out 0000 0000 b power - up 3k 1k o pen open open 1k 4.96v 0000 0000 b fan off 3k 1k open open open 1k 0v 0000 0001 b lowest 3k 1k open o pen 3.6k 783 5.99v 0000 0010 b 2 nd lowest 3k 1k open 1.8k open 643 7.03v 0000 0011 b 3 rd lowest 3k 1k o pen 1.8k 3.6k 545 8.06v 0000 0100 b medium 3k 1k 1k open open 500 8.68v 0000 0101 b 3 rd highest 3k 1k 1k open 3.6k 439 9.71v 0000 0110 b 2 nd highest 3k 1k 1k 1.8k open 391 10.75v 0000 0111 b highest 3k 1k 1k 1.8k 3.6k 353 11.78v downloaded from: http:///
micrel, inc. mic74 september 30 , 20 14 19 revision 3.0 package information and recommended landing pattern ( 9 ) 16 -pin qsop ( qs ) note: 9. package information is correct as of the publication date. for updates and most current information, go to www.micrel.com . downloaded from: http:///
micrel, inc. mic74 september 30 , 20 14 20 revision 3.0 micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944 - 0800 fax +1 (408) 474 - 1000 web http://www.micrel.com micrel, inc. is a leading global manufacturer of ic solutions for the worldwide high perfor mance linear and power, l an, and timing & communications markets. the companys products include advanced mixed - signal, analog & power semiconductors; high - performance communication, clock management, mems - based clock oscillators & crystal - less clock generators, ethernet switches, and physical layer transceiver ics. company customers include leading manufacturers of enterprise, consumer, industrial, mobi le, telecommunications, automotive, and computer products. corporation headquarters and state - of - the - art wafer fabrication facilities are located in san jose, ca, with regional sales and support offices and advanced technology design centers situated throughout the americas, europe, and asia. additionally, the company maintains an extensive network of distributors and reps worldwide. micrel makes no representations or warranties with respect to the accuracy or co mpleteness of the information furnished in this datasheet. this information is not intended as a warranty and micrel does not assume responsibility for its use. micrel reserves the right t o change circuitry, specifications and descriptions at any time without notice. no license, whether express , implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in micrels terms and condition s of sale for such products, micrel assumes no liability whatsoever, and micrel disclaims any express or implied warranty relating to the sale and/or u se of micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any pat ent, copyright, or other intellectual prope rty right. micrel products are not designed or authorized for use as components in life support appliances , devices or systems where malfunction of a product can reasonably be expected to result in personal injury. life support devices or systems are device s or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expec ted to result in a significant injury to the user. a purchasers use or sale of micrel products for use in life support appliances, devices or systems is a purchasers own risk and purc haser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 20 00 micrel, incorporated. downloaded from: http:///

▲Up To Search▲

Price & Availability of MIC7400-0005YFL

	To Download MIC7400-0005YFL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .